Programmable interconnect architectures are used in user-programmable arrays of logic cells, also referred to as "Field Programmable Gate Arrays (FPGAs)," as well as in dedicated programmable interconnect chips, microprocessors, digital signal processor cores, etc.
Such programmable interconnect architectures typically consist of a network of conductive nodes, programmable passive switches, and programmable or non-programmable repeater circuits. An interconnection from one conductive node to another is obtained by programming the intermediate passive switches to be conducting, and by programming each repeater circuit to be propagating and enhancing the signal from one of its terminals to another. The signal enhancement through a repeater circuit consists of driving the output with a low-impedance version of the logic signal at the input.
The repeater circuits are necessary to limit the propagation delay and the signal rise/fall time in cases where the interconnection contains many passive switches in sequence. The delay through such a network can be approximately modeled as an "RC-chain," and hence both propagation delay and rise/fall time are roughly proportional to the square of the number of switches traversed. The network of switches and repeaters can be optimized to have minimum worst case propagation delay, and an acceptable signal rise/fall time, under a given layout area constraint. The optimization consists of finding the best combination of repeater circuit sizing, switch sizing, and switch-to-repeater ratio. The switch-to-repeater ratio is the worst case number of switches between repeaters in the path of an interconnection.
The design trade-offs may be explained as follows. As the switches are made larger, their on-resistance becomes smaller, but the capacitance added to the conductive nodes becomes larger. Second order factors such as fringe capacitance and the non-linear voltage dependence of the on-resistance of the switches, as well as the size of the repeater, must be considered to find the best switch size. Placing repeaters at every conductive node is possible if there is no area constraint. However, repeaters have an inherent propagation delay. When placed at every node, the repeater propagation delay dominates the total propagation delay.
In a realistic programmable interconnect architecture, a layout area constraint must be considered. In bi-directional, two-dimensional programmable interconnect architectures, such as the ones used in FPGAs, the repeater area is very large: the bi-directionality and the two-dimensionality may require a redundancy of a factor two or larger in the number of three-state buffers: not more than half the buffers, but usually fewer, are actually used when programmed. The fact that three-state buffers are employed implies large circuits and additional area overhead because of the need for memory cells in the repeaters.
In conclusion, the area and performance of programmable bi-directional interconnect architectures may be improved efficiently by employing a bi-directional repeater circuit with a small propagation delay and a small area.
The Design and Analysis of VLSI Circuits (L. Glasser and D. Dobberpuhl, Addison-Wesley Publishing Company, Reading, Mass., 1985, p. 420, FIG. 8.5) shows a carry chain employing a precharge PMOS transistor and an evaluation circuit with feedback on each intermediate node of the carry chain. However, that circuit is directed to providing a short propagation delay in a dynamic logic unidirectional carry chain. It does not address the use of a complementary pair of evaluation circuits for the speed-up of both high-to-low and low-to-high transitions. Furthermore, it does not address the use of a delay circuit in order to obtain a circuit that works independent of a clock. Finally, it does not address the use of such a circuit in a programmable interconnect architecture, and it does not address the use of such a precharge and evaluation circuit for bi-directional signal propagation.
Journal article "A 20-kbit Associative Memory LSI for Artificial Intelligence Machines" by T. Ogura et al., in the IEEE Journal of Solid State Circuits, Vol. 24, No. 4, August, 1989, p. 1018, FIG. 6, shows an accelerator circuit employing feedback, using a PMOS transistor as a detection circuit and an NMOS transistor as an evaluation circuit. However, that circuit is different from the current invention, and is directed to speeding up the discharging of a match line in a content addressable memory cell, in a dynamic logic circuit. It does not address the use of a complementary pair of evaluation circuits for the speed-up of both high-to-low and low-to-high transitions. Furthermore, it does not address the use of a delay circuit in order to obtain a circuit that works independent of a clock. Finally, it does not address the use of such a circuit in a programmable interconnect architecture, and it does not address the use of such a precharge and evaluation circuit for bi-directional signal propagation.
U.S. Pat. No. 4,498,021 to M. Uya discloses a booster for transmitting digital signals. However, that circuit is directed to speeding up transitions on a single bus wire, and does not address the problem of bi-directional interconnections through programmable switches with an appreciable resistance. In addition, the circuit of Uya uses separate threshold voltages to turn on and off the drivers of the booster circuits, instead of using a predetermined delay. This not only results in additional circuitry, but results in less reliable operation compared to the current invention. More in particular, the use of Uya's circuit at intermediate nodes of a network of programmable switches is less reliable since the booster circuit is turned off when the voltage at the node reaches the threshold voltage for deactivation, regardless of the potential at the node attached to the subsequent booster circuit. In the case where a rising transition is propagated, if a first booster circuit then is turned off prematurely and fails to bring the node of a subsequent booster circuit past the activation threshold voltage, the charge stored in the further nodes will cause the node of the first booster to drop back, below the activation threshold voltage for the opposite transition, and initiate oscillations. Since the resistances and capacitances are relatively large in practical implementations of such networks using MOS transistors, and since it is impractical to provide detection circuits with threshold voltages close to the power supply or the ground level in MOS technology, Uya's circuit is not guaranteed to operate correctly in such a programmable interconnect architecture. In the present invention, on the other hand, the designer can choose the predetermined delay to be long enough such that subsequent speed-up circuits are guaranteed to be activated.
U.S. Pat. No. 5,202,593 to T. Huang et al. discloses a bi-directional bus repeater that does not need a direction setting control signal. However, that circuit is directed to providing automatic sensing of the signal propagation direction in a bus repeater and does not provide the improvement in the rise/fall time of the input signal offered by the current invention, which has concurrently active drivers on both the input and output network nodes.